Fix UART RX module instantiation and update build script for correct file references

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Gamenight77

2025-05-07 11:07:42 +02:00

parent 83c40bee28

commit f990a6f6d3

3 changed files with 809 additions and 14 deletions

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Semaine_4/UART/IP/verilog/rxuartlite.v Normal file

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