forked from tanchou/Verilog
Fix UART RX module instantiation and update build script for correct file references
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@@ -17,23 +17,22 @@ module top_uart_loopback (
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end
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// === UART RX ===
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other_uart_rx uart_rx_inst (
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.clk(clk),
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.rst_n(1'b1),
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.rx_pin(rx),
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.rx_data_valid(rx_received),
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.rx_data_ready(1'b1),
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.rx_data(rx_data)
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rxuartlite uart_rx_inst (
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.i_clk(clk),
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.i_reset(1'b0),
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.i_uart_rx(rx),
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.o_wr(rx_received),
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.o_data(rx_data)
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);
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// === UART TX ===
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other_uart_tx uart_tx_inst (
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uart_tx uart_tx_inst (
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.clk(clk),
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.rst_n(1'b1),
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.tx_data(tx_data),
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.tx_data_valid(tx_enable),
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.tx_data_ready(tx_ready),
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.tx_pin(tx)
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.rst_p(1'b0),
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.data(data_const),
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.tx_enable(tx_enable),
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.tx_ready(tx_ready),
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.tx(tx)
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);
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// === FSM avec délai ===
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