Fix UART RX module instantiation and update build script for correct file references

Semaine_4/UART/scripts/build.bat

@@ -19,7 +19,7 @@ if not exist runs (
 )
 
 echo === Étape 1 : Synthèse avec Yosys ===
-yosys -p "read_verilog -sv src/verilog/%TOP%1.v IP/verilog/other_rx.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
+yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/other_rx.v IP/verilog/rxuartlite.v IP/verilog/other_tx.v src/verilog/uart_rx.v src/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
 if errorlevel 1 goto error
 
 echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===

Semaine_4/UART/src/verilog/top_uart_loopback.v

@@ -17,23 +17,22 @@ module top_uart_loopback (
     end
 
     // === UART RX ===
-    other_uart_rx uart_rx_inst (
+    rxuartlite uart_rx_inst (
-        .clk(clk),
+        .i_clk(clk),
-        .rst_n(1'b1),
+        .i_reset(1'b0),
-        .rx_pin(rx),
+        .i_uart_rx(rx),
-        .rx_data_valid(rx_received),
+        .o_wr(rx_received),
-        .rx_data_ready(1'b1),
+        .o_data(rx_data)
-        .rx_data(rx_data)
     );
 
     // === UART TX ===
-    other_uart_tx uart_tx_inst (
+    uart_tx uart_tx_inst (
         .clk(clk),
-        .rst_n(1'b1),
+        .rst_p(1'b0),
-        .tx_data(tx_data),
+        .data(data_const),
-        .tx_data_valid(tx_enable),
+        .tx_enable(tx_enable),
-        .tx_data_ready(tx_ready),
+        .tx_ready(tx_ready),
-        .tx_pin(tx)
+        .tx(tx)
     );
 
     // === FSM avec délai ===