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forked from tanchou/Verilog

5 Commits

Author SHA1 Message Date
Gamenight77
1d6677d67d Init du DHT11 Interface 2025-05-14 09:22:07 +02:00
Gamenight77
0faab53c30 uart v3 2025-05-02 11:03:14 +02:00
Gamenight77
596d47d356 Refactor ws2812_driver module for improved timing and data handling 2025-04-28 14:30:29 +02:00
Gamenight77
1811301ef2 Refactor ultrasonic_fpga and ultrasonic_sensor modules for improved functionality
- Initialized registers in ultrasonic_fpga to avoid undefined behavior.
- Modified state machine in ultrasonic_fpga to include a COMPUTE state for better echo measurement handling.
- Adjusted echo counting logic to ensure accurate distance calculation.
- Updated ultrasonic_sensor to allow for a more flexible trigger pulse timing by reducing the threshold for valid triggers.
2025-04-28 10:33:36 +02:00
Gamenight77
505f71974e New Week 2025-04-28 09:22:17 +02:00