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forked from tanchou/Verilog
Commit Graph

9 Commits

Author SHA1 Message Date
Gamenight77
168431849b Code FPGA fonctionnel 2025-05-27 15:36:40 +02:00
Gamenight77
4e16bb3cbe Fix timer conditions in DHT11 state machine for signal detection 2025-05-27 13:45:58 +02:00
Gamenight77
d69a0a4753 Adjust timer threshold for signal detection in DHT11 interface 2025-05-27 13:38:33 +02:00
Gamenight77
425cc8d00c Refactor DHT11 interface to support 16-bit temperature and humidity data, update checksum handling, and improve state machine logic 2025-05-27 13:34:59 +02:00
Gamenight77
286ba6b33c Enhance DHT11 interface and update measurement delay in top module 2025-05-27 12:51:00 +02:00
Gamenight77
68000def79 Remove unnecessary blank line in dht11_interface module 2025-05-27 10:31:52 +02:00
Gamenight77
7d7a6e16d8 Patch 2025-05-27 10:30:30 +02:00
Gamenight77
35f84d9d16 recodage de lundi 2025-05-27 10:12:31 +02:00
Gamenight77
a02d6e7d22 init semaine 7 2025-05-25 19:04:56 +02:00