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forked from tanchou/Verilog
Commit Graph

4 Commits

Author SHA1 Message Date
Gamenight77
abef18227c Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality 2025-05-07 09:46:43 +02:00
Gamenight77
1ca3456ab8 Création de la structure du uart fifo 2025-05-06 09:42:26 +02:00
Gamenight77
e0a54fb42a Add LED indication for RX signal in top_uart_loopback module 2025-05-05 14:54:40 +02:00
Gamenight77
589c36ed83 Loopback ne fonctionne pas 2025-05-05 14:52:01 +02:00