forked from tanchou/Verilog
Add LED indication for RX signal in top_uart_loopback module
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@@ -41,6 +41,7 @@ module top_uart_loopback (
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reg state = IDLE;
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always @(posedge clk) begin
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leds[5] <= rx;
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case (state)
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IDLE: begin
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tx_enable <= 0;
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