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forked from tanchou/Verilog
Commit Graph

5 Commits

Author SHA1 Message Date
Gamenight77
99e259f672 MAJ FIFO -> turn wire rd_data into register 2025-05-09 10:27:13 +02:00
Gamenight77
cd14d82add patch 2025-05-09 09:20:56 +02:00
Gamenight77
a162a2a1bb Update LED display logic to show received data instead of received signal 2025-05-09 09:15:44 +02:00
Gamenight77
a792f85adf loopback fonctionne avec le rxuartlite 2025-05-09 09:15:28 +02:00
Gamenight77
83c40bee28 Fix build script and update state machine in UART loopback module 2025-05-07 10:39:52 +02:00