forked from tanchou/Verilog
190 lines
4.5 KiB
Verilog
190 lines
4.5 KiB
Verilog
`default_nettype none
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module top_uart_loopback (
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input wire clk, // 27 MHz
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input wire rx,
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output wire tx,
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output wire [5:0] leds
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);
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wire rx_received;
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wire [7:0] rx_data;
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reg [7:0] tx_data;
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reg tx_enable;
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reg rx_enable;
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wire tx_ready;
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/* // === UART RX ===
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uart_rx uart_rx_inst (
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.clk(clk),
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.rst_p(1'b0),
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.rx_pin(rx),
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.rx_received(tx_enable),
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.rx_received(rx_received),
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.rx_enable(1'b1),
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.rx_enable(tx_ready),
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//.rx_data(rx_data)
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.rx_data(rx_data)
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);*/
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rxuartlite uart_rx_inst (
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.i_clk(clk),
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.i_reset(1'b0),
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.i_uart_rx(rx),
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.o_wr(rx_received),
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.o_data(rx_data)
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);
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reg [7:0] stored_data;
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reg [7:0] data_const = 8'h31;
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//initial data_const = ;
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wire r;
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// === UART TX ===
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uart_tx uart_tx_inst (
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.clk(clk),
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.rst_p(1'b0),
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.data(tx_data),
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.tx_enable(tx_enable),
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.tx_ready(tx_ready),
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.tx(tx)
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);
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/* other_uart_tx uart_tx_inst (
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.clk(clk),
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.rst_n(1'b1),
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.tx_data(data_const),
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.tx_data_valid(tx_enable),
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.tx_data_ready(tx_ready),
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.tx_pin(tx)
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);*/
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/* reg delay_active = 0;
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reg [31:0] delay_counter = 0;
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localparam DELAY_CYCLES = 27000000 / 2; // 0.5 second delay at 27 MHz
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reg data_ready = 0;
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// Store received data and trigger delay
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always @(posedge clk) begin
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begin
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// Capture new received data
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if (rx_received && !data_ready) begin
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stored_data <= rx_data;
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data_ready <= 1'b1;
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delay_active <= 1'b1;
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delay_counter <= DELAY_CYCLES;
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end
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// Countdown delay
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if (delay_active) begin
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if (delay_counter > 0) begin
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delay_counter <= delay_counter - 1;
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end
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else begin
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delay_active <= 1'b0;
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end
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end
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end
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end
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// Control transmission
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always @(posedge clk) begin
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begin
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tx_enable <= 1'b0; // Default assignment
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// Start transmission when delay completes and UART is ready
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if (data_ready && !delay_active && tx_ready && !tx_enable) begin
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tx_enable <= 1'b1;
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data_ready <= 1'b0; // Clear flag after starting transmission
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end
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end
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end */
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localparam CLK_FREQ = 27_000_000; // 27 MHz
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localparam DATA_BYTE = 8'h31; // ASCII '1'
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// State machine to continuously send the byte
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reg [31:0] delay_counter;
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localparam DELAY_CYCLES = CLK_FREQ / 2; // 0.5 second delay between transmissions
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always @(posedge clk) begin
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begin
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// Default assignments
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tx_enable <= 1'b0;
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if (tx_ready && delay_counter == 0) begin
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// Start new transmission
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tx_enable <= 1'b1;
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data_const <= DATA_BYTE;
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tx_data <= rx_data;
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//leds[5:0] <= rx_data[5:0]; // Display received data on LEDs
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leds[5] <= rx_received;
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delay_counter <= DELAY_CYCLES;
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end
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else if (delay_counter > 0) begin
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// Count down delay
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delay_counter <= delay_counter - 1;
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end
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end
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end
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/*
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// === FSM avec délai ===
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localparam IDLE = 0, WAIT = 1, SEND = 2;
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reg [1:0] state = IDLE;
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reg [8:0] delay_counter = 0;
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always @(posedge clk) begin
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leds[5] <= rx;
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leds[4] <= tx;
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case (state)
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IDLE: begin
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tx_enable <= 0;
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delay_counter <= 0;
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if (rx_received && tx_ready) begin
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tx_data <= rx_data;
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state <= WAIT;
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leds[0] <= 0;
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leds[1] <= 1;
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end
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end
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WAIT: begin
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delay_counter <= delay_counter + 1;
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if (delay_counter == 8'd400 && tx_ready) begin
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tx_enable <= 1;
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state <= SEND;
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end else begin
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tx_enable <= 0;
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end
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leds[0] <= 1;
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leds[1] <= 0;
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end
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SEND: begin
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tx_enable <= 0;
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state <= IDLE;
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leds[0] <= 0;
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leds[1] <= 0; // Envoi terminé
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end
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endcase
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end
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*/
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endmodule |