1
0
forked from tanchou/Verilog
Files
Verilog_Louis/Introduction/counter/tangnano20k.cst
Gamenight77 66fa5b2650 Add initial design files for 27 MHz clock counter
- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.
2025-04-15 08:59:40 +02:00

15 lines
350 B
Plaintext

# Horloge 27 MHz (souvent sur PIN4)
IO_LOC "clk" 4;
IO_PORT "clk" IO_TYPE=LVCMOS33;
# Bouton KEY1 (utilisé ici comme btn1 pour reset)
IO_LOC "btn1" 88;
IO_PORT "btn1" IO_TYPE=LVCMOS33;
# LEDs (pour afficher le compteur)
IO_LOC "count[0]" 15;
IO_LOC "count[1]" 16;
IO_LOC "count[2]" 17;
IO_LOC "count[3]" 18;
IO_PORT "count[3:0]" IO_TYPE=LVCMOS33;