verlan/Verilog_Louis

forked from tanchou/Verilog

Files

History

Louis TANCHOU ebe6cefda4 Update S4 Uart FIFO

2025-06-05 15:59:12 +02:00

..

Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality

2025-05-07 09:46:43 +02:00

Update S4 Uart FIFO

2025-06-05 15:59:12 +02:00

Update testbench and simulation scripts to use a unified output file name for GTKWave

2025-05-19 09:31:53 +02:00

Update S4 Uart FIFO

2025-06-05 15:59:12 +02:00

Update testbench and simulation scripts to use a unified output file name for GTKWave

2025-05-19 09:31:53 +02:00

.gitignore

Création de la structure du uart fifo

2025-05-06 09:42:26 +02:00

project.bat

Création de la structure du uart fifo

2025-05-06 09:42:26 +02:00

README.md

Add README for UART loopback issue and delay explanation

2025-05-09 11:58:55 +02:00

README.md

UART loopback

Probleme 3 octest de retard quand vous envoyer un octet, vous recevez le loopback de 3 octets plus tot. il faut attendre 3 octets avant de le recevoir