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Verilog_Louis
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Verilog_Louis
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Semaine_4
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Louis TANCHOU
ebe6cefda4
Update S4 Uart FIFO
2025-06-05 15:59:12 +02:00
..
FIFO
Sa a l'air de fonctionner
2025-05-16 10:34:32 +02:00
UART
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
UART_FIFO
Update S4 Uart FIFO
2025-06-05 15:59:12 +02:00
UART_ULTRASON
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00