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Verilog_Louis
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Verilog_Louis
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Semaine_4
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UART_ULTRASON
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Gamenight77
30bbe27510
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00
..
constraints
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00
IP
/verilog
Fix build script and update state machine in UART loopback module
2025-05-07 10:39:52 +02:00
scripts
Implement UART and ultrasonic sensor integration with FIFO for data transmission
2025-05-07 10:27:17 +02:00
src
/verilog
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00
tests
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00
.gitignore
Implement UART and ultrasonic sensor integration with FIFO for data transmission
2025-05-07 10:27:17 +02:00
project.bat
Implement UART and ultrasonic sensor integration with FIFO for data transmission
2025-05-07 10:27:17 +02:00
Gamenight77