forked from tanchou/Verilog
c8f108e01d
- Implemented the ultrasonic_fpga module to handle ultrasonic sensor operations including triggering and measuring distance. - Added a simulation testbench (ultrasonic_sim) to validate the functionality of the ultrasonic_fpga module. - The module includes state management for triggering the sensor and measuring the echo duration to calculate distance. - Simulation includes initialization, triggering the sensor, and checking the output distance.
2329 lines
17 KiB
Plaintext
2329 lines
17 KiB
Plaintext
$date
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Wed Apr 16 13:26:52 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb_ultrasonic_fpga $end
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$var wire 1 ! trig_out $end
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$var wire 16 " distance [15:0] $end
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$var reg 1 # clk $end
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$var reg 1 $ echo $end
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$var reg 1 % rst $end
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$var reg 1 & start $end
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$var reg 64 ' t_end [63:0] $end
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$var reg 64 ( t_start [63:0] $end
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$scope module uut $end
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$var wire 1 # clk $end
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$var wire 1 $ echo $end
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$var wire 1 % rst $end
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$var wire 1 & start $end
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$var parameter 32 ) CLK_FREQ $end
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$var parameter 32 * DIST_DIVISOR $end
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$var parameter 32 + DONE $end
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$var parameter 32 , IDLE $end
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$var parameter 32 - MEASURE_ECHO $end
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$var parameter 32 . TRIG $end
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$var parameter 32 / TRIG_DURATION_CYCLES $end
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$var parameter 32 0 WAIT_ECHO $end
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$var reg 16 1 distance [15:0] $end
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$var reg 16 2 echo_counter [15:0] $end
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$var reg 3 3 state [2:0] $end
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$var reg 9 4 trig_counter [8:0] $end
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$var reg 1 ! trig_out $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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b10 0
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b1 *
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b1100110111111110011000000 )
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$end
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#0
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