forked from tanchou/Verilog
Add Ultrasonic FPGA module and simulation testbench
- Implemented the ultrasonic_fpga module to handle ultrasonic sensor operations including triggering and measuring distance. - Added a simulation testbench (ultrasonic_sim) to validate the functionality of the ultrasonic_fpga module. - The module includes state management for triggering the sensor and measuring the echo duration to calculate distance. - Simulation includes initialization, triggering the sensor, and checking the output distance.
This commit is contained in:
Gamenight77
@@ -1,6 +1,12 @@
|
||||
# Verilog
|
||||
|
||||
## Command
|
||||
|
||||
|
||||
## Commands
|
||||
Compile code
|
||||
iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v
|
||||
|
||||
|
||||
### Upload on fpga
|
||||
yosys -p "synth_ecp5 -json design.json" counter.v
|
||||
nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc
|
||||
|
||||
73
Semaine 1/Ultrasonic/tb_ultrasonic_fpga.v
Normal file
73
Semaine 1/Ultrasonic/tb_ultrasonic_fpga.v
Normal file
@@ -0,0 +1,73 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module tb_ultrasonic_fpga;
|
||||
|
||||
reg clk = 0;
|
||||
reg rst = 1;
|
||||
reg start = 0;
|
||||
reg echo = 0;
|
||||
wire trig_out;
|
||||
wire [15:0] distance;
|
||||
|
||||
time t_start, t_end;
|
||||
|
||||
// Clock 27MHz => periode = 37.037ns
|
||||
always #18 clk = ~clk;
|
||||
|
||||
ultrasonic_fpga uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.start(start),
|
||||
.echo(echo),
|
||||
.trig_out(trig_out),
|
||||
.distance(distance)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("ultrasonic.vcd");
|
||||
$dumpvars(0, tb_ultrasonic_fpga);
|
||||
|
||||
// Reset
|
||||
#100;
|
||||
rst = 0;
|
||||
|
||||
// Start
|
||||
#100;
|
||||
start = 1;
|
||||
#40;
|
||||
start = 0;
|
||||
|
||||
wait (trig_out == 1);
|
||||
t_start = $time;
|
||||
|
||||
// Attendre qu'il redescende
|
||||
wait (trig_out == 0);
|
||||
t_end = $time;
|
||||
|
||||
$display("Trig HIGH duration: %0dns", t_end - t_start);
|
||||
|
||||
if ((t_end - t_start) >= 9500 && (t_end - t_start) <= 10500) begin
|
||||
$display("Trigger signal is high for 10us.");
|
||||
|
||||
#10;
|
||||
echo = 1;
|
||||
|
||||
#5800;// Echo dure 5800ns (≈ 100 cycles @ 27MHz => ≈ 100 cm aller-retour)
|
||||
echo = 0;
|
||||
end else begin
|
||||
$display("Trigger signal is NOT high for 10us.");
|
||||
end
|
||||
|
||||
#500;
|
||||
|
||||
// Affiche la distance
|
||||
if (distance > 0) begin
|
||||
$display("Distance measured: %d cm", distance);
|
||||
end else begin
|
||||
$display("No distance measured.");
|
||||
end
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
2328
Semaine 1/Ultrasonic/ultrasonic.vcd
Normal file
2328
Semaine 1/Ultrasonic/ultrasonic.vcd
Normal file
File diff suppressed because it is too large
Load Diff
71
Semaine 1/Ultrasonic/ultrasonic_fpga.v
Normal file
71
Semaine 1/Ultrasonic/ultrasonic_fpga.v
Normal file
@@ -0,0 +1,71 @@
|
||||
module ultrasonic_fpga #(
|
||||
parameter integer CLK_FREQ = 27_000_000 // frequence de clk en Hz
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire start, // signal de declenchement
|
||||
input wire echo, // retour du capteur
|
||||
output reg trig_out, // signal envoye au capteur
|
||||
output reg [15:0] distance // distance mesuree
|
||||
);
|
||||
|
||||
reg [2:0] state;
|
||||
reg [8:0] trig_counter;
|
||||
reg [15:0] echo_counter;
|
||||
|
||||
localparam IDLE = 0, TRIG = 1, WAIT_ECHO = 2, MEASURE_ECHO = 3, DONE = 4;
|
||||
|
||||
// Constantes dépendantes de CLK_FREQ
|
||||
localparam integer TRIG_DURATION_CYCLES = CLK_FREQ / 100_000; // 10us
|
||||
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion µs -> cm
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
state <= IDLE;
|
||||
trig_out <= 0;
|
||||
trig_counter <= 0;
|
||||
echo_counter <= 0;
|
||||
distance <= 0;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE: begin
|
||||
if (start) begin
|
||||
state <= TRIG;
|
||||
end
|
||||
end
|
||||
|
||||
TRIG: begin
|
||||
if (trig_counter < TRIG_DURATION_CYCLES) begin
|
||||
trig_out <= 1;
|
||||
trig_counter <= trig_counter + 1;
|
||||
end else begin
|
||||
trig_out <= 0;
|
||||
trig_counter <= 0;
|
||||
state <= WAIT_ECHO;
|
||||
end
|
||||
end
|
||||
|
||||
WAIT_ECHO: begin
|
||||
if (echo) begin
|
||||
echo_counter <= 0;
|
||||
state <= MEASURE_ECHO;
|
||||
end
|
||||
end
|
||||
|
||||
MEASURE_ECHO: begin
|
||||
if (echo) begin
|
||||
echo_counter <= echo_counter + 1;
|
||||
end else begin
|
||||
distance <= (echo_counter*1000) / DIST_DIVISOR;
|
||||
state <= DONE;
|
||||
end
|
||||
end
|
||||
|
||||
DONE: begin
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
265
Semaine 1/Ultrasonic/ultrasonic_sim
Normal file
265
Semaine 1/Ultrasonic/ultrasonic_sim
Normal file
@@ -0,0 +1,265 @@
|
||||
#!
|
||||
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision - 12;
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
|
||||
S_000002569854ec30 .scope module, "tb_ultrasonic_fpga" "tb_ultrasonic_fpga" 2 3;
|
||||
.timescale -9 -12;
|
||||
v00000256985b7a50_0 .var "clk", 0 0;
|
||||
v00000256985b72d0_0 .net "distance", 15 0, v000002569854e7f0_0; 1 drivers
|
||||
v00000256985b7870_0 .var "echo", 0 0;
|
||||
v00000256985b7cd0_0 .var "rst", 0 0;
|
||||
v00000256985b7f50_0 .var "start", 0 0;
|
||||
v00000256985b7910_0 .var "t_end", 63 0;
|
||||
v00000256985b7af0_0 .var "t_start", 63 0;
|
||||
v00000256985b7d70_0 .net "trig_out", 0 0, v00000256985b7370_0; 1 drivers
|
||||
E_000002569854ae50 .event anyedge, v00000256985b7370_0;
|
||||
S_000002569854edc0 .scope module, "uut" "ultrasonic_fpga" 2 17, 3 1 0, S_000002569854ec30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst";
|
||||
.port_info 2 /INPUT 1 "start";
|
||||
.port_info 3 /INPUT 1 "echo";
|
||||
.port_info 4 /OUTPUT 1 "trig_out";
|
||||
.port_info 5 /OUTPUT 16 "distance";
|
||||
P_0000025698560660 .param/l "CLK_FREQ" 0 3 2, +C4<00000001100110111111110011000000>;
|
||||
P_0000025698560698 .param/l "DIST_DIVISOR" 1 3 20, +C4<00000000000000000000000000000001>;
|
||||
P_00000256985606d0 .param/l "DONE" 1 3 16, +C4<00000000000000000000000000000100>;
|
||||
P_0000025698560708 .param/l "IDLE" 1 3 16, +C4<00000000000000000000000000000000>;
|
||||
P_0000025698560740 .param/l "MEASURE_ECHO" 1 3 16, +C4<00000000000000000000000000000011>;
|
||||
P_0000025698560778 .param/l "TRIG" 1 3 16, +C4<00000000000000000000000000000001>;
|
||||
P_00000256985607b0 .param/l "TRIG_DURATION_CYCLES" 1 3 19, +C4<00000000000000000000000100001110>;
|
||||
P_00000256985607e8 .param/l "WAIT_ECHO" 1 3 16, +C4<00000000000000000000000000000010>;
|
||||
v000002569854ef50_0 .net "clk", 0 0, v00000256985b7a50_0; 1 drivers
|
||||
v000002569854e7f0_0 .var "distance", 15 0;
|
||||
v000002569854c1a0_0 .net "echo", 0 0, v00000256985b7870_0; 1 drivers
|
||||
v00000256985b74b0_0 .var "echo_counter", 15 0;
|
||||
v00000256985b7b90_0 .net "rst", 0 0, v00000256985b7cd0_0; 1 drivers
|
||||
v00000256985b7c30_0 .net "start", 0 0, v00000256985b7f50_0; 1 drivers
|
||||
v00000256985b7050_0 .var "state", 2 0;
|
||||
v00000256985b77d0_0 .var "trig_counter", 8 0;
|
||||
v00000256985b7370_0 .var "trig_out", 0 0;
|
||||
E_000002569854af10 .event posedge, v00000256985b7b90_0, v000002569854ef50_0;
|
||||
.scope S_000002569854edc0;
|
||||
T_0 ;
|
||||
%wait E_000002569854af10;
|
||||
%load/vec4 v00000256985b7b90_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_0.0, 8;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%assign/vec4 v00000256985b7050_0, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000256985b7370_0, 0;
|
||||
%pushi/vec4 0, 0, 9;
|
||||
%assign/vec4 v00000256985b77d0_0, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000256985b74b0_0, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v000002569854e7f0_0, 0;
|
||||
%jmp T_0.1;
|
||||
T_0.0 ;
|
||||
%load/vec4 v00000256985b7050_0;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.2, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.3, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.4, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.5, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.6, 6;
|
||||
%jmp T_0.7;
|
||||
T_0.2 ;
|
||||
%load/vec4 v00000256985b7c30_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_0.8, 8;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%assign/vec4 v00000256985b7050_0, 0;
|
||||
T_0.8 ;
|
||||
%jmp T_0.7;
|
||||
T_0.3 ;
|
||||
%load/vec4 v00000256985b77d0_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 270, 0, 32;
|
||||
%jmp/0xz T_0.10, 5;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000256985b7370_0, 0;
|
||||
%load/vec4 v00000256985b77d0_0;
|
||||
%addi 1, 0, 9;
|
||||
%assign/vec4 v00000256985b77d0_0, 0;
|
||||
%jmp T_0.11;
|
||||
T_0.10 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000256985b7370_0, 0;
|
||||
%pushi/vec4 0, 0, 9;
|
||||
%assign/vec4 v00000256985b77d0_0, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%assign/vec4 v00000256985b7050_0, 0;
|
||||
T_0.11 ;
|
||||
%jmp T_0.7;
|
||||
T_0.4 ;
|
||||
%load/vec4 v000002569854c1a0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_0.12, 8;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000256985b74b0_0, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%assign/vec4 v00000256985b7050_0, 0;
|
||||
T_0.12 ;
|
||||
%jmp T_0.7;
|
||||
T_0.5 ;
|
||||
%load/vec4 v000002569854c1a0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_0.14, 8;
|
||||
%load/vec4 v00000256985b74b0_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v00000256985b74b0_0, 0;
|
||||
%jmp T_0.15;
|
||||
T_0.14 ;
|
||||
%load/vec4 v00000256985b74b0_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%div;
|
||||
%pad/u 16;
|
||||
%assign/vec4 v000002569854e7f0_0, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%assign/vec4 v00000256985b7050_0, 0;
|
||||
T_0.15 ;
|
||||
%jmp T_0.7;
|
||||
T_0.6 ;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%assign/vec4 v00000256985b7050_0, 0;
|
||||
%jmp T_0.7;
|
||||
T_0.7 ;
|
||||
%pop/vec4 1;
|
||||
T_0.1 ;
|
||||
%jmp T_0;
|
||||
.thread T_0;
|
||||
.scope S_000002569854ec30;
|
||||
T_1 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000256985b7a50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000256985b7cd0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000256985b7f50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000256985b7870_0, 0, 1;
|
||||
%end;
|
||||
.thread T_1;
|
||||
.scope S_000002569854ec30;
|
||||
T_2 ;
|
||||
%delay 18000, 0;
|
||||
%load/vec4 v00000256985b7a50_0;
|
||||
%inv;
|
||||
%store/vec4 v00000256985b7a50_0, 0, 1;
|
||||
%jmp T_2;
|
||||
.thread T_2;
|
||||
.scope S_000002569854ec30;
|
||||
T_3 ;
|
||||
%vpi_call 2 27 "$dumpfile", "ultrasonic.vcd" {0 0 0};
|
||||
%vpi_call 2 28 "$dumpvars", 32'sb00000000000000000000000000000000, S_000002569854ec30 {0 0 0};
|
||||
%delay 100000, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000256985b7cd0_0, 0, 1;
|
||||
%delay 100000, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000256985b7f50_0, 0, 1;
|
||||
%delay 40000, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000256985b7f50_0, 0, 1;
|
||||
T_3.0 ;
|
||||
%load/vec4 v00000256985b7d70_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%cmpi/ne 1, 0, 1;
|
||||
%jmp/0xz T_3.1, 6;
|
||||
%wait E_000002569854ae50;
|
||||
%jmp T_3.0;
|
||||
T_3.1 ;
|
||||
%vpi_func 2 41 "$time" 64 {0 0 0};
|
||||
%store/vec4 v00000256985b7af0_0, 0, 64;
|
||||
T_3.2 ;
|
||||
%load/vec4 v00000256985b7d70_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 4;
|
||||
%cmpi/ne 1, 0, 1;
|
||||
%jmp/0xz T_3.3, 6;
|
||||
%wait E_000002569854ae50;
|
||||
%jmp T_3.2;
|
||||
T_3.3 ;
|
||||
%vpi_func 2 45 "$time" 64 {0 0 0};
|
||||
%store/vec4 v00000256985b7910_0, 0, 64;
|
||||
%load/vec4 v00000256985b7910_0;
|
||||
%load/vec4 v00000256985b7af0_0;
|
||||
%sub;
|
||||
%vpi_call 2 47 "$display", "Trig HIGH duration: %0dns", S<0,vec4,u64> {1 0 0};
|
||||
%load/vec4 v00000256985b7910_0;
|
||||
%load/vec4 v00000256985b7af0_0;
|
||||
%sub;
|
||||
%cmpi/u 9500, 0, 64;
|
||||
%flag_inv 5; GE is !LT
|
||||
%flag_get/vec4 5;
|
||||
%jmp/0 T_3.6, 5;
|
||||
%load/vec4 v00000256985b7910_0;
|
||||
%load/vec4 v00000256985b7af0_0;
|
||||
%sub;
|
||||
%cmpi/u 10500, 0, 64;
|
||||
%flag_get/vec4 4;
|
||||
%flag_get/vec4 5;
|
||||
%or;
|
||||
%and;
|
||||
T_3.6;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.4, 8;
|
||||
%vpi_call 2 50 "$display", "Trigger signal is high for 10us." {0 0 0};
|
||||
%delay 10000, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000256985b7870_0, 0, 1;
|
||||
%delay 5800000, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000256985b7870_0, 0, 1;
|
||||
%jmp T_3.5;
|
||||
T_3.4 ;
|
||||
%vpi_call 2 58 "$display", "Trigger signal is NOT high for 10us." {0 0 0};
|
||||
T_3.5 ;
|
||||
%delay 500000, 0;
|
||||
%load/vec4 v00000256985b72d0_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 0, 0, 32;
|
||||
%flag_or 5, 4; GT is !LE
|
||||
%flag_inv 5;
|
||||
%jmp/0xz T_3.7, 5;
|
||||
%vpi_call 2 65 "$display", "Distance measured: %d cm", v00000256985b72d0_0 {0 0 0};
|
||||
%jmp T_3.8;
|
||||
T_3.7 ;
|
||||
%vpi_call 2 67 "$display", "No distance measured." {0 0 0};
|
||||
T_3.8 ;
|
||||
%vpi_call 2 70 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_3;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb_ultrasonic_fpga.v";
|
||||
"ultrasonic_fpga.v";
|
||||
Reference in New Issue
Block a user