forked from tanchou/Verilog
72 lines
2.2 KiB
Verilog
72 lines
2.2 KiB
Verilog
module ultrasonic_fpga #(
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parameter integer CLK_FREQ = 27_000_000 // frequence de clk en Hz
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)(
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input wire clk,
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input wire rst,
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input wire start, // signal de declenchement
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input wire echo, // retour du capteur
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output reg trig_out, // signal envoye au capteur
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output reg [8:0] distance // distance mesuree
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);
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reg [2:0] state;
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reg [8:0] trig_counter;
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reg [15:0] echo_counter;
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localparam IDLE = 0, TRIG = 1, WAIT_ECHO = 2, MEASURE_ECHO = 3, DONE = 4;
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// Constantes dépendantes de CLK_FREQ
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localparam integer TRIG_DURATION_CYCLES = CLK_FREQ / 100_000; // 10us
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localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion µs -> cm
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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state <= IDLE;
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trig_out <= 0;
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trig_counter <= 0;
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echo_counter <= 0;
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distance <= 0;
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end else begin
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case (state)
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IDLE: begin
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if (start) begin
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state <= TRIG;
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end
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end
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TRIG: begin
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if (trig_counter < TRIG_DURATION_CYCLES) begin
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trig_out <= 1;
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trig_counter <= trig_counter + 1;
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end else begin
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trig_out <= 0;
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trig_counter <= 0;
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state <= WAIT_ECHO;
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end
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end
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WAIT_ECHO: begin
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if (echo) begin
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echo_counter <= 0;
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state <= MEASURE_ECHO;
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end
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end
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MEASURE_ECHO: begin
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if (echo) begin
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echo_counter <= echo_counter + 1;
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end else begin
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distance <= (echo_counter*1000) / DIST_DIVISOR;
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state <= DONE;
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end
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end
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DONE: begin
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state <= IDLE;
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end
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endcase
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end
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end
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endmodule
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