forked from tanchou/Verilog
25 lines
589 B
Markdown
25 lines
589 B
Markdown
# Verilog
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## [Semaine 1](/Semaine_1/)
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## [Semaine 2](/Semaine_2/)
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## Cheat sheet
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### Commands
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Compile code
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iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v
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#### Upload on fpga
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rem https://github.com/YosysHQ/apicula
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yosys -p "read_verilog blink_led.v; synth_gowin -json blink_led_c.json"
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set DEVICE=GW2AR-LV18QN88C8/I7
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set BOARD=tangnano20k
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nextpnr-himbaechel --json blink_led_c.json --write pnr_blink_led.json --device %DEVICE% --vopt cst=blink_led.cst --vopt family=GW2A-18C
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gowin_pack -d %DEVICE% -o blink_led_c.fs pnr_blink_led.json
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openfpgaloader -b %BOARD% blink_led_c.fs |