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Verilog_Louis/Introduction/counter/tb_counter.v
Gamenight77 7bd92ebe98 counter
2025-03-22 09:50:52 +01:00

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417 B
Verilog

module tb_counter;
reg clk;
reg rst;
wire [3:0] count;
counter counter_inst(
.clk(clk),
.rst(rst),
.count(count)
);
always #5 clk = ~clk;
initial begin
clk <= 0;
rst <= 0;
#20 rst = 1;
#80 rst = 0;
#50 rst = 1;
#20 $finish;
end
always begin
#5 clk = ~clk;
end
endmodule