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Verilog_Louis
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Gamenight77
2c08e4bbbe
Remove unnecessary closing parenthesis in counter module
2025-03-22 10:11:16 +01:00
Introduction
/counter
Remove unnecessary closing parenthesis in counter module
2025-03-22 10:11:16 +01:00
README.md
Initial commit
2025-03-22 09:16:50 +01:00
README.md
Verilog
Description
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Readme
218
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Verilog
75.7%
Tcl
9.8%
Batchfile
5%
Shell
3.5%
Python
3.1%
Other
2.8%