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Verilog_Louis
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3541476e9aefa26882fde7b5e86392c66c9b0f2b
Verilog_Louis
/
Semaine_7
/
ESP32
/
leds_commands
/
tests
/
pyhton
History
Louis TANCHOU
3541476e9a
vLundi juin
2025-06-02 14:42:40 +02:00
..
connectESP.py
vLundi juin
2025-06-02 14:42:40 +02:00
connectESPV2.py
Add connectESPV2.py for socket communication and hex input handling
2025-05-28 10:32:27 +02:00
