forked from tanchou/Verilog
37 lines
516 B
Verilog
37 lines
516 B
Verilog
`default_nettype none
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module example1 (
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input wire clk, // global clock
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input wire [7:0] edx,
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output reg strobe, // output strobe
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output wire [7:0] res
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);
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localparam WIDTH=4;
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reg[WIDTH-1:0] count = 0;
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always_comb begin
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strobe = &count;
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end
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always_ff @(posedge clk) begin
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count <= count + 1;
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end
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assign res = edx + 5;
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endmodule
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/*
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module top_module (
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input in1,
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input in2,
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input in3,
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output out);
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always_comb
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out = ~(in1 ^ in2) ^ in3;
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endmodule
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*/ |