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verlan
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Verilog_Louis
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54bf6df85b9dbdea10eeb27c09d0509c6f1d2ee7
Verilog_Louis
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Semaine_4
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Gamenight77
1006b77e95
Update testbench and simulation scripts to use a unified output file name for GTKWave
2025-05-19 09:31:53 +02:00
..
FIFO
Sa a l'air de fonctionner
2025-05-16 10:34:32 +02:00
UART
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
UART_FIFO
Update testbench and simulation scripts to use a unified output file name for GTKWave
2025-05-19 09:31:53 +02:00
UART_ULTRASON
ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer
2025-05-12 12:15:52 +02:00