forked from tanchou/Verilog
Louis TANCHOU
54bf6df85b
- Implemented a FIFO buffer in Verilog for data storage. - Created a simplified UART transmitter (txuartlite) for serial communication. - Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow. - Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission. - Added a testbench (tb_dht11) for simulating the DHT11 module functionality. - Updated README with project description and command references. - Created build and simulation scripts for both Linux and Windows environments. - Added constraints file for hardware configuration. - Implemented a state machine for managing measurement and data transmission.
18 lines
293 B
Bash
Executable File
18 lines
293 B
Bash
Executable File
#!/bin/bash
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echo "=== Simulation avec Icarus Verilog ==="
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OUT="runs/sim.vvp"
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TOP="tb_dht11"
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DIRS=("src/verilog" "tests/verilog")
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FILES=()
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for dir in "${DIRS[@]}"; do
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for file in "$dir"/*.v; do
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FILES+=("$file")
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done
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done
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iverilog -g2012 -o "$OUT" -s "$TOP" "${FILES[@]}"
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vvp "$OUT"
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