forked from tanchou/Verilog
Louis TANCHOU
54bf6df85b
- Implemented a FIFO buffer in Verilog for data storage. - Created a simplified UART transmitter (txuartlite) for serial communication. - Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow. - Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission. - Added a testbench (tb_dht11) for simulating the DHT11 module functionality. - Updated README with project description and command references. - Created build and simulation scripts for both Linux and Windows environments. - Added constraints file for hardware configuration. - Implemented a state machine for managing measurement and data transmission.
4 lines
65 B
Batchfile
4 lines
65 B
Batchfile
@echo off
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echo === Lancement de GTKWave ===
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gtkwave runs/sim.vcd
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