forked from tanchou/Verilog
Louis TANCHOU
54bf6df85b
- Implemented a FIFO buffer in Verilog for data storage. - Created a simplified UART transmitter (txuartlite) for serial communication. - Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow. - Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission. - Added a testbench (tb_dht11) for simulating the DHT11 module functionality. - Updated README with project description and command references. - Created build and simulation scripts for both Linux and Windows environments. - Added constraints file for hardware configuration. - Implemented a state machine for managing measurement and data transmission.
29 lines
544 B
Batchfile
29 lines
544 B
Batchfile
@echo off
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echo === Simulation avec Icarus Verilog ===
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setlocal enabledelayedexpansion
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:: Dossier de sortie
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set OUT=runs/sim.vvp
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:: Top-level testbench module
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set TOP=tb_dht11
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:: Répertoires contenant des fichiers .v
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set DIRS=src/verilog tests/verilog IP/verilog
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:: Variable pour stocker les fichiers
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set FILES=
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:: Boucle sur chaque dossier
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for %%D in (%DIRS%) do (
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for %%F in (%%D\*.v) do (
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set FILES=!FILES! %%F
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)
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)
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:: Compilation avec Icarus Verilog
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iverilog -g2012 -o %OUT% -s %TOP% %FILES%
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endlocal
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vvp runs/sim.vvp |