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Verilog_Louis/Semaine 1/UART/memo.png
Gamenight77 55f9161dfa Add UART transmitter module and testbench
- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate.
- Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock.
- Created a backup of the previous testbench (uart_tx_tb_old) for reference.
2025-04-17 10:56:16 +02:00

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/verlan/Verilog_Louis/raw/commit/55f9161dfa7a7bfc4611e812d1837765555b2a24/Semaine%201/UART/memo.png