This website requires JavaScript.
Explore
Help
Sign In
verlan
/
Verilog_Louis
Watch
1
Star
0
Fork
0
You've already forked Verilog_Louis
forked from
tanchou/Verilog
Code
Pull Requests
Activity
Files
65cf0e8232044577f1d95b44bce1f35560db0077
Verilog_Louis
/
Semaine 1
History
Gamenight77
65cf0e8232
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00
..
Capteur_recule_avec_deux_broche
Add testbench for top_ultrasonic_led module
2025-04-16 14:58:04 +02:00
Capteur_recule_bidirectionel
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00
Python_UART
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00
UART
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00
top_ultrason_uart.v
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00