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Verilog_Louis
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65cf0e8232044577f1d95b44bce1f35560db0077
Verilog_Louis
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Semaine 1
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Python_UART
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Gamenight77
65cf0e8232
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00
..
led_uart.py
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00
read_rx.py
Refactor UART testbench and top-level modules; remove old testbench files, enhance UART communication in top_ultrason_uart, and implement LED control via UART in top_led_uart. Add Python scripts for UART communication and data reading.
2025-04-17 18:00:54 +02:00