forked from tanchou/Verilog
6dfd8768a0
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the functionality of the `top_ultrasonic_led` module. - Included necessary signal definitions and event triggers for clock, reset, start, echo, and trigger signals. - Implemented a state machine to handle the ultrasonic measurement process and LED display logic. - Added simulation parameters for distance measurement and LED control. - Integrated VPI calls for waveform dumping and simulation control.
27 lines
645 B
Verilog
27 lines
645 B
Verilog
module top_ultrasonic_led (
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input wire clk,
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input wire rst,
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input wire start, // bouton de déclenchement
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inout wire sig, // broche unique pour trigger + echo
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output wire [5:0] leds // LEDs pour affichage distance
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);
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wire [8:0] distance;
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// Module de mesure (version bidirectionnelle du capteur)
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ultrasonic_fpga_onewire ultrasonic_inst (
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.clk(clk),
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.rst(rst),
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.start(start),
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.sig(sig),
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.distance(distance)
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);
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// Module d'affichage LEDs
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distance_display_led led_display_inst (
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.distance(distance),
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.leds(leds)
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);
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endmodule
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