forked from tanchou/Verilog
7a2fbc0195
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the `top_ultrasonic_led` module. - Defined the necessary signals and events for testing the ultrasonic sensor functionality. - Implemented the main test sequence including triggering the ultrasonic sensor and monitoring the output LEDs based on distance measurements. - Included timing and state management for accurate simulation of the ultrasonic sensor behavior.
62 lines
1.0 KiB
Verilog
62 lines
1.0 KiB
Verilog
`timescale 1ns/1ps
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module tb_top_ultrasonic_led;
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reg clk;
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reg rst;
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reg start;
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reg echo;
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wire trig;
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wire [5:0] leds;
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// Instance du module top
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top_ultrasonic_led uut (
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.clk(clk),
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.rst(rst),
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.start(start),
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.echo(echo),
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.trig(trig),
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.leds(leds)
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);
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always #18.5 clk = ~clk;
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initial begin
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// Initialisation
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$dumpfile("top_ultrasonic_led.vcd");
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$dumpvars(0, tb_top_ultrasonic_led);
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clk = 0;
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rst = 1;
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start = 0;
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echo = 0;
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#100;
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rst = 0;
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#50;
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start = 1;
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#20;
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start = 0;
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// Attente du signal trig
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wait (trig == 1);
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$display("TRIG HIGH at %t", $time);
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wait (trig == 0);
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$display("TRIG LOW at %t", $time);
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repeat (500) @(posedge clk);
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echo = 1;
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#12000
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echo = 0;
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repeat (500) @(posedge clk);
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$display("Leds allumer : %b", leds);
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$finish;
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end
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endmodule
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