forked from tanchou/Verilog
7a2fbc0195
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the `top_ultrasonic_led` module. - Defined the necessary signals and events for testing the ultrasonic sensor functionality. - Implemented the main test sequence including triggering the ultrasonic sensor and monitoring the output LEDs based on distance measurements. - Included timing and state management for accurate simulation of the ultrasonic sensor behavior.
Verilog
Commands
Compile code iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v
Upload on fpga
yosys -p "synth_ecp5 -json design.json" counter.v nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc