forked from tanchou/Verilog
32 lines
507 B
Verilog
32 lines
507 B
Verilog
module tb_counter;
|
|
reg clk;
|
|
reg rst;
|
|
wire [3:0] count;
|
|
|
|
counter counter_inst(
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.count(count)
|
|
);
|
|
|
|
always #5 clk = ~clk;
|
|
|
|
initial begin
|
|
$dumpfile("dump.vcd"); // Nom du fichier de traces
|
|
$dumpvars(0, counter_inst);
|
|
|
|
clk <= 0;
|
|
rst <= 0;
|
|
|
|
|
|
#20 rst = 1;
|
|
#80 rst = 0;
|
|
#50 rst = 1;
|
|
|
|
#20 $finish;
|
|
end
|
|
|
|
always begin
|
|
#5 clk = ~clk;
|
|
end
|
|
endmodule |