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Verilog_Louis/Introduction/counter/top.v
Gamenight77 66fa5b2650 Add initial design files for 27 MHz clock counter
- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.
2025-04-15 08:59:40 +02:00

13 lines
183 B
Verilog

module top (
input wire clk,
input wire btn1,
output wire [3:0] count
);
counter uut (
.clk(clk),
.btn1(btn1),
.count(count)
);
endmodule