forked from tanchou/Verilog
66fa5b2650
- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs. - Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.
22 lines
485 B
Makefile
22 lines
485 B
Makefile
TOP = top
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DEVICE = GW2AR-18
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all: $(TOP).fs
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$(TOP).json: $(TOP).v counter.v
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yosys -p "read_verilog $(TOP).v counter.v; synth_gowin -top $(TOP) -json $(TOP).json"
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$(TOP).asc: $(TOP).json tangnano20k.cst
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nextpnr-gowin --json $(TOP).json --device $(DEVICE) --cst tangnano20k.cst --write $(TOP).asc
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$(TOP).fs: $(TOP).asc
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gowin_pack $(TOP).asc $(TOP).fs
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prog: $(TOP).fs
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openFPGALoader -b tangnano20k $(TOP).fs
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clean:
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rm -f $(TOP).json $(TOP).asc $(TOP).fs
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.PHONY: all prog clean
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