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verlan
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Verilog_Louis
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e086ba8ef0d87887fe9a3cc31c8162260de993b1
Verilog_Louis
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Semaine_4
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Gamenight77
e086ba8ef0
Loopback fifo fonctionne mais avec 3 valeur de décalage
2025-05-09 11:39:40 +02:00
..
FIFO
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
UART
MAJ FIFO -> turn wire rd_data into register
2025-05-09 10:27:13 +02:00
UART_FIFO
Loopback fifo fonctionne mais avec 3 valeur de décalage
2025-05-09 11:39:40 +02:00
UART_ULTRASON
Add WAIT state to FSM and implement delay mechanism in UART module
2025-05-07 18:07:45 +02:00