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verlan
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Verilog_Louis
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ec1c69cf8f4baf244a729b45484865efc093247d
Verilog_Louis
/
Semaine_4
/
FIFO
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Gamenight77
aaebf22d48
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
..
constraints
Add UART TX module and testbench, update scripts and constraints
2025-05-05 15:23:44 +02:00
scripts
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
src
/verilog
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
tests
/verilog
Tb for fifo working fine
2025-05-06 09:14:59 +02:00
.gitignore
Add UART TX module and testbench, update scripts and constraints
2025-05-05 15:23:44 +02:00
project.bat
Add UART TX module and testbench, update scripts and constraints
2025-05-05 15:23:44 +02:00
