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Verilog_Louis/Help/presentation_examples/blink/src/verilog/blink_top.v
Gamenight77 f5e73d7379 struct
2025-05-02 15:51:18 +02:00

14 lines
156 B
Verilog

module blink_top
(
input wire clk,
output wire led
);
blink #(
.CLK_SPEED(27_000_000)
) blink_inst (
.clk(clk),
.led(led)
);
endmodule