Verilog_Louis/Semaine_4/FIFO/src/verilog/fifo.v

 module uart_tx #(
	parameter       DETPH = 16,
	parameter       WIDTH = 8
)(
    input wire              clk,
    input wire              wr_en,
    input wire[WIDTH-1:0]   wr_data,
    input wire              rd_en,
    output wire[WIDTH-1:0]  rd_data,

    output wire             full,
    output wire             empty,
);

    reg [WIDTH-1:0]         fifo[0:DETPH-1];
    reg [3:0]               wr_ptr;
    reg [3:0]               rd_ptr;
    reg [3:0]               count;

    assign full = (count == DETPH);
    assign empty = (count == 0);
    assign rd_data = fifo[rd_ptr];

    always @(posedge clk) begin
        if (wr_en && !full) begin
            fifo[wr_ptr] <= wr_data;
            wr_ptr <= (wr_ptr + 1) % DETPH;
            count <= count + 1;
        end

        if (rd_en && !empty) begin
            rd_ptr <= (rd_ptr + 1) % DETPH;
            count <= count - 1;
        end
    end
    
endmodule