Verilog_Louis/README.md

# Verilog

## Command
### Upload on fpga
yosys -p "synth_ecp5 -json design.json" counter.v
nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc
Initial commit 2025-03-22 09:16:50 +01:00			`# Verilog`

Add initial design files for 27 MHz clock counter - Created tangnano20k.cst to define I/O locations for clock, button, and LEDs. - Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output. 2025-04-15 08:59:40 +02:00			`## Command`
			`### Upload on fpga`
			`yosys -p "synth_ecp5 -json design.json" counter.v`
			`nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc`