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Verilog_Louis/Semaine_4/UART_FIFO/scripts/gtkwave.bat

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Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00
@echo off
echo === Lancement de GTKWave ===
Refactor UART FIFO implementation: update top-level module and integrate RX/TX FIFO functionality
2025-05-07 09:46:43 +02:00
gtkwave runs/uart_rx_fifo.vcd
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