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verlan
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Verilog_Louis
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e086ba8ef0d87887fe9a3cc31c8162260de993b1
Verilog_Louis
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Semaine_4
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UART_FIFO
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scripts
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gtkwave.bat
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Création de la structure du uart fifo
2025-05-06 09:42:26 +02:00
@
echo
off
echo
=== Lancement de GTKWave ===
Loopback fifo fonctionne mais avec 3 valeur de décalage
2025-05-09 11:39:40 +02:00
gtkwave runs/uart_fifo.vcd
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