forked from tanchou/Verilog
Refactor distance data type from 15 bits to 9 bits in ultrasonic_fpga module and update related testbench for consistency
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@@ -7,7 +7,7 @@ module tb_ultrasonic_fpga;
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reg start = 0;
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reg echo = 0;
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wire trig_out;
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wire [15:0] distance;
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wire [8:0] distance;
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time t_start, t_end;
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