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forked from tanchou/Verilog

Refactor distance data type from 15 bits to 9 bits in ultrasonic_fpga module and update related testbench for consistency

This commit is contained in:
Gamenight77
2025-04-16 14:03:48 +02:00
parent a00122b595
commit 079159bdb8
6 changed files with 392 additions and 2 deletions

View File

@@ -7,7 +7,7 @@ module tb_ultrasonic_fpga;
reg start = 0;
reg echo = 0;
wire trig_out;
wire [15:0] distance;
wire [8:0] distance;
time t_start, t_end;