Fix clock period comment in testbench for clarity

2025-04-16 13:32:08 +02:00
parent c8f108e01d
commit a00122b595
1 changed files with 1 additions and 1 deletions
--- a/1/Ultrasonic/tb_ultrasonic_fpga.v
+++ b/1/Ultrasonic/tb_ultrasonic_fpga.v
@@ -11,7 +11,7 @@ module tb_ultrasonic_fpga;

    time t_start, t_end;

-    // Clock 27MHz => periode = 37.037ns
+    // Clock 27MHz => periode = 37ns
    always #18 clk = ~clk;

    ultrasonic_fpga uut (