Init du DHT11 Interface

Semaine_5/DHT11/.gitignore

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+runs
+.vscode
+workspace.code-workspace
+*.pyc
+.idea

Semaine_5/DHT11/README.md

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+# ULTRASON VIA UART
+
+## Description
+This project is designed to control an ultrasonic sensor using UART communication. The ultrasonic sensor is used to measure distance, and the data is transmitted via UART to a connected device.
+
+## Commands
+0x01: Start one mesurement of the distance.
+0x02: Start continuous mesurement of the distance.
+0x03: Stop continuous mesurement of the distance.

Semaine_5/DHT11/constraints/dht11_interface.cst

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+IO_LOC "tx" 69;
+IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+
+IO_LOC "rx" 70;
+IO_PORT "rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+
+IO_LOC "clk" 4;
+IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+
+IO_LOC "ultrason_sig" 73;
+IO_PORT "ultrason_sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+
+IO_LOC "leds[0]" 15;
+IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[1]" 16;
+IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[2]" 17;
+IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[3]" 18;
+IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[4]" 19;
+IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_LOC "leds[5]" 20;
+IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;

Semaine_5/DHT11/project.bat

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+@call c:\oss-cad-suite\environment.bat 
+@echo off
+if "%1"=="sim" call scripts\simulate.bat
+if "%1"=="wave" call scripts\gtkwave.bat
+if "%1"=="clean" call scripts\clean.bat
+if "%1"=="build" call scripts\build.bat

Semaine_5/DHT11/scripts/build.bat

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+@echo off
+setlocal
+
+rem === Aller à la racine du projet ===
+cd /d %~dp0\..
+
+rem === Config de base ===
+set DEVICE=GW2AR-LV18QN88C8/I7
+set BOARD=tangnano20k
+set TOP=top_uart_ultrason_command
+set CST_FILE=%TOP%.cst
+set JSON_FILE=runs/%TOP%.json
+set PNR_JSON=runs/pnr_%TOP%.json
+set BITSTREAM=runs/%TOP%.fs
+
+rem === Créer le dossier runs si nécessaire ===
+if not exist runs (
+    mkdir runs
+)
+
+echo === Étape 1 : Synthèse avec Yosys ===
+yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
+if errorlevel 1 goto error
+
+echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===
+nextpnr-himbaechel --json %JSON_FILE% --write %PNR_JSON% --device %DEVICE% --vopt cst=constraints/%CST_FILE% --vopt family=GW2A-18C
+if errorlevel 1 goto error
+
+echo === Étape 3 : Packing avec gowin_pack ===
+gowin_pack -d %DEVICE% -o %BITSTREAM% %PNR_JSON%
+if errorlevel 1 goto error
+
+echo === Étape 4 : Flash avec openFPGALoader ===
+openFPGALoader -b %BOARD% %BITSTREAM%
+if errorlevel 1 goto error
+
+echo === Compilation et flash réussis ===
+goto end
+
+:error
+echo === Une erreur est survenue ===
+
+:end
+endlocal
+pause

Semaine_5/DHT11/scripts/clean.bat

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+@echo off
+echo === Nettoyage du dossier runs ===
+rd /s /q runs
+mkdir runs

Semaine_5/DHT11/scripts/gtkwave.bat

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+@echo off
+echo === Lancement de GTKWave ===
+gtkwave runs/wave.vcd

Semaine_5/DHT11/scripts/simulate.bat

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+@echo off
+echo === Simulation avec Icarus Verilog ===
+setlocal enabledelayedexpansion
+
+:: Dossier de sortie
+set OUT=runs/sim.vvp
+
+:: Top-level testbench module
+set TOP=dht11_interface
+
+:: Répertoires contenant des fichiers .v
+set DIRS=src/verilog tests/verilog IP/verilog
+
+:: Variable pour stocker les fichiers
+set FILES=
+
+:: Boucle sur chaque dossier
+for %%D in (%DIRS%) do (
+    for %%F in (%%D\*.v) do (
+        set FILES=!FILES! %%F
+    )
+)
+
+:: Compilation avec Icarus Verilog
+iverilog -g2012 -o %OUT% -s %TOP% %FILES%
+
+endlocal
+
+vvp runs/sim.vvp

Semaine_5/DHT11/src/verilog/dht11_interface.v

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+module dht11_interface (
+    input wire          i_clk, // 27 MHz
+    inout wire          io_dht11_sig,
+    output wire         o_dht11_data_ready,
+    output wire [7:0]   o_temp_data,
+    output wire [7:0]   o_hum_data,
+    output wire         o_dht11_error
+);
+
+    // === DHT11 INTERFACE ===
+    // Le module DHT11 est connecté à la broche io_dht11_sig.
+    // La communication se fait en mode bidirectionnel.
+
+    wire sig_dir;
+    wire sig_out;
+    
+    assign io_dht11_sig = sig_dir ? sig_out : 1'bz;
+
+
+    // === FSM ===
+    localparam  IDLE            = 3'd0, // Pull up la ligne
+
+                START           = 3'd1, // Pull low 18ms
+                WAIT_RESPONSE   = 3'd2, // Release la ligne (entre 20 et 40us)
+
+                READ_HUM_INT    = 3'd3, 
+                READ_HUM_DEC    = 3'd4;
+                READ_TEMP_INT   = 3'd5, 
+                READ_TEMP_DEC   = 3'd6,
+                READ_CHECKSUM   = 3'd7, // Last 8 bits of {1st Byte + 2nd Byte + 3rd Byte+ 4th Byte}
+
+                DONE            = 3'd8;
+               
+
+endmodule

Semaine_5/DHT11/tests/verilog/tb_dht11.v

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+`timescale 1ns/1ps
+
+module tb_dht11;
+
+    reg clk = 0;
+    always #18.5 clk = ~clk; // Génère une clock 27 MHz
+
+    // === Simulation du module DHT11 ===
+
+
+    // === Module DHT11 INTERFACE ===
+
+
+    // === TEST SEQUENCE ===
+    initial begin
+        $dumpfile("runs/wave.vcd");
+        $dumpvars(0, tb_dht11);
+
+        $display("==== Start DHT11 Test ====");
+        
+        
+
+        $display("==== End DHT11 Test ====");
+        $finish;
+    end
+
+endmodule