forked from tanchou/Verilog
Remove unnecessary closing parenthesis in counter module
This commit is contained in:
@@ -11,6 +11,5 @@ module counter (
|
||||
else
|
||||
count <= count + 1;
|
||||
end
|
||||
);
|
||||
|
||||
endmodule
|
Reference in New Issue
Block a user