Remove unnecessary closing parenthesis in counter module · 2c08e4bbbe - Verilog_Louis - Grond

verlan/Verilog_Louis

forked from tanchou/Verilog

Remove unnecessary closing parenthesis in counter module

This commit is contained in:

Gamenight77

2025-03-22 10:11:16 +01:00

parent 7bd92ebe98

commit 2c08e4bbbe

1 changed files with 0 additions and 1 deletions

									
										Introduction/counter/counter.v
									
		-1
	
												View File
												
				@@ -11,6 +11,5 @@ module counter (

				        else

				            count <= count + 1;

				    end

				);

				endmodule