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forked from tanchou/Verilog

Remove unnecessary closing parenthesis in counter module

This commit is contained in:
Gamenight77
2025-03-22 10:11:16 +01:00
parent 7bd92ebe98
commit 2c08e4bbbe

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@@ -11,6 +11,5 @@ module counter (
else
count <= count + 1;
end
);
endmodule