forked from tanchou/Verilog
Add UART transmitter module and testbench
- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate. - Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock. - Created a backup of the previous testbench (uart_tx_tb_old) for reference.
This commit is contained in:
Binary file not shown.
Before Width: | Height: | Size: 9.3 KiB After Width: | Height: | Size: 40 KiB |
Reference in New Issue
Block a user