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Add UART transmitter module and testbench

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- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate.
- Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock.
- Created a backup of the previous testbench (uart_tx_tb_old) for reference.
This commit is contained in:
Gamenight77
2025-04-17 10:56:16 +02:00
parent d46530f32d
commit 55f9161dfa
14 changed files with 40177 additions and 0 deletions
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Semaine 1/UART/top_uart_tx_tb Normal file
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#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_00000229acd190a0 .scope module, "tb_top_uart_rx_tx" "tb_top_uart_rx_tx" 2 3;
.timescale -9 -12;
P_00000229accd6e80 .param/l "BAUD_RATE" 0 2 6, +C4<00000000000000011100001000000000>;
P_00000229accd6eb8 .param/l "CLK_FREQ" 0 2 5, +C4<00000001100110111111110011000000>;
L_00000229acd19630 .functor BUFZ 1, v00000229acd79f10_0, C4<0>, C4<0>, C4<0>;
v00000229acd79b50_0 .var "clk", 0 0;
v00000229acd790b0_0 .var "data_in", 7 0;
v00000229acd79bf0_0 .net "data_out", 7 0, v00000229acd0de70_0; 1 drivers
v00000229acd79d30_0 .net "rx", 0 0, L_00000229acd19630; 1 drivers
v00000229acd79150_0 .var "start", 0 0;
v00000229acd7ad40_0 .net "tx", 0 0, v00000229acd79f10_0; 1 drivers
v00000229acd7bd80_0 .net "valid", 0 0, v00000229acd79470_0; 1 drivers
E_00000229accfc720 .event anyedge, v00000229acd79470_0;
S_00000229acd19230 .scope module, "uut" "top_uart_rx_tx" 2 21, 3 1 0, S_00000229acd190a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "start";
.port_info 2 /INPUT 8 "data_in";
.port_info 3 /INPUT 1 "rx";
.port_info 4 /OUTPUT 8 "data_out";
.port_info 5 /OUTPUT 1 "valid";
.port_info 6 /OUTPUT 1 "tx";
P_00000229accd6c60 .param/l "BAUD_RATE" 0 3 12, +C4<00000000000000011100001000000000>;
P_00000229accd6c98 .param/l "CLK_FREQ" 0 3 11, +C4<00000001100110111111110011000000>;
v00000229acd79830_0 .net "clk", 0 0, v00000229acd79b50_0; 1 drivers
v00000229acd79650_0 .net "data_in", 7 0, v00000229acd790b0_0; 1 drivers
v00000229acd79ab0_0 .net "data_out", 7 0, v00000229acd0de70_0; alias, 1 drivers
v00000229acd79fb0_0 .net "rx", 0 0, L_00000229acd19630; alias, 1 drivers
v00000229acd796f0_0 .net "start", 0 0, v00000229acd79150_0; 1 drivers
v00000229acd79970_0 .net "tx", 0 0, v00000229acd79f10_0; alias, 1 drivers
v00000229acd79790_0 .net "valid", 0 0, v00000229acd79470_0; alias, 1 drivers
S_00000229acd193c0 .scope module, "rx_instance" "uart_rx" 3 27, 4 1 0, S_00000229acd19230;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rx";
.port_info 2 /OUTPUT 8 "data";
.port_info 3 /OUTPUT 1 "valid";
.port_info 4 /OUTPUT 1 "ready";
P_00000229acd0dce0 .param/l "BAUD_RATE" 0 4 10, +C4<00000000000000011100001000000000>;
P_00000229acd0dd18 .param/l "BIT_PERIOD" 1 4 12, +C4<00000000000000000000000011101010>;
P_00000229acd0dd50 .param/l "CLK_FREQ" 0 4 9, +C4<00000001100110111111110011000000>;
P_00000229acd0dd88 .param/l "DATA" 1 4 16, C4<10>;
P_00000229acd0ddc0 .param/l "IDLE" 1 4 14, C4<00>;
P_00000229acd0ddf8 .param/l "START" 1 4 15, C4<01>;
P_00000229acd0de30 .param/l "STOP" 1 4 17, C4<11>;
v00000229acd00f00_0 .var "bit_index", 3 0;
v00000229acd00fa0_0 .net "clk", 0 0, v00000229acd79b50_0; alias, 1 drivers
v00000229accd6a10_0 .var "clk_count", 15 0;
v00000229acd0de70_0 .var "data", 7 0;
v00000229acd0df10_0 .var "ready", 0 0;
v00000229acd79dd0_0 .net "rx", 0 0, L_00000229acd19630; alias, 1 drivers
v00000229acd798d0_0 .var "rx_data", 7 0;
v00000229acd79290_0 .var "state", 1 0;
v00000229acd79470_0 .var "valid", 0 0;
E_00000229accfc4e0 .event posedge, v00000229acd00fa0_0;
S_00000229acd0dfb0 .scope module, "tx_instance" "uart_tx" 3 17, 5 1 0, S_00000229acd19230;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "start";
.port_info 2 /INPUT 8 "data";
.port_info 3 /OUTPUT 1 "tx";
.port_info 4 /OUTPUT 1 "busy";
P_00000229acbec9b0 .param/l "BAUD_RATE" 0 5 10, +C4<00000000000000011100001000000000>;
P_00000229acbec9e8 .param/l "BIT_PERIOD" 1 5 11, +C4<00000000000000000000000011101010>;
P_00000229acbeca20 .param/l "CLK_FREQ" 0 5 9, +C4<00000001100110111111110011000000>;
P_00000229acbeca58 .param/l "DATA" 1 5 15, C4<10>;
P_00000229acbeca90 .param/l "IDLE" 1 5 13, C4<00>;
P_00000229acbecac8 .param/l "START" 1 5 14, C4<01>;
P_00000229acbecb00 .param/l "STOP" 1 5 16, C4<11>;
v00000229acd79a10_0 .var "bit_index", 3 0;
v00000229acd793d0_0 .var "busy", 0 0;
v00000229acd79e70_0 .net "clk", 0 0, v00000229acd79b50_0; alias, 1 drivers
v00000229acd79510_0 .var "clk_count", 15 0;
v00000229acd79c90_0 .net "data", 7 0, v00000229acd790b0_0; alias, 1 drivers
v00000229acd79330_0 .net "start", 0 0, v00000229acd79150_0; alias, 1 drivers
v00000229acd795b0_0 .var "state", 1 0;
v00000229acd79f10_0 .var "tx", 0 0;
v00000229acd791f0_0 .var "tx_data", 7 0;
.scope S_00000229acd0dfb0;
T_0 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000229acd79f10_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000229acd793d0_0, 0, 1;
%pushi/vec4 0, 0, 2;
%store/vec4 v00000229acd795b0_0, 0, 2;
%pushi/vec4 0, 0, 4;
%store/vec4 v00000229acd79a10_0, 0, 4;
%pushi/vec4 0, 0, 16;
%store/vec4 v00000229acd79510_0, 0, 16;
%pushi/vec4 0, 0, 8;
%store/vec4 v00000229acd791f0_0, 0, 8;
%end;
.thread T_0;
.scope S_00000229acd0dfb0;
T_1 ;
%wait E_00000229accfc4e0;
%load/vec4 v00000229acd795b0_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_1.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_1.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_1.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_1.3, 6;
%jmp T_1.4;
T_1.0 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000229acd793d0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000229acd79f10_0, 0;
%load/vec4 v00000229acd79330_0;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_1.7, 9;
%load/vec4 v00000229acd793d0_0;
%nor/r;
%and;
T_1.7;
%flag_set/vec4 8;
%jmp/0xz T_1.5, 8;
%load/vec4 v00000229acd79c90_0;
%assign/vec4 v00000229acd791f0_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000229acd79a10_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000229acd79510_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000229acd793d0_0, 0;
%pushi/vec4 1, 0, 2;
%assign/vec4 v00000229acd795b0_0, 0;
T_1.5 ;
%jmp T_1.4;
T_1.1 ;
%load/vec4 v00000229acd79510_0;
%pad/u 32;
%cmpi/u 233, 0, 32;
%jmp/0xz T_1.8, 5;
%load/vec4 v00000229acd79510_0;
%addi 1, 0, 16;
%assign/vec4 v00000229acd79510_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000229acd79f10_0, 0;
%jmp T_1.9;
T_1.8 ;
%pushi/vec4 2, 0, 2;
%assign/vec4 v00000229acd795b0_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000229acd79510_0, 0;
T_1.9 ;
%jmp T_1.4;
T_1.2 ;
%load/vec4 v00000229acd79510_0;
%pad/u 32;
%cmpi/u 233, 0, 32;
%jmp/0xz T_1.10, 5;
%load/vec4 v00000229acd79510_0;
%addi 1, 0, 16;
%assign/vec4 v00000229acd79510_0, 0;
%jmp T_1.11;
T_1.10 ;
%load/vec4 v00000229acd79a10_0;
%pad/u 32;
%cmpi/u 8, 0, 32;
%jmp/0xz T_1.12, 5;
%load/vec4 v00000229acd791f0_0;
%load/vec4 v00000229acd79a10_0;
%part/u 1;
%assign/vec4 v00000229acd79f10_0, 0;
%load/vec4 v00000229acd79a10_0;
%addi 1, 0, 4;
%assign/vec4 v00000229acd79a10_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000229acd79510_0, 0;
%jmp T_1.13;
T_1.12 ;
%pushi/vec4 3, 0, 2;
%assign/vec4 v00000229acd795b0_0, 0;
T_1.13 ;
T_1.11 ;
%jmp T_1.4;
T_1.3 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000229acd79f10_0, 0;
%load/vec4 v00000229acd79510_0;
%pad/u 32;
%cmpi/u 233, 0, 32;
%jmp/0xz T_1.14, 5;
%load/vec4 v00000229acd79510_0;
%addi 1, 0, 16;
%assign/vec4 v00000229acd79510_0, 0;
%jmp T_1.15;
T_1.14 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000229acd79510_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000229acd793d0_0, 0;
%pushi/vec4 0, 0, 2;
%assign/vec4 v00000229acd795b0_0, 0;
T_1.15 ;
%jmp T_1.4;
T_1.4 ;
%pop/vec4 1;
%jmp T_1;
.thread T_1;
.scope S_00000229acd193c0;
T_2 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000229acd79470_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000229acd0df10_0, 0, 1;
%pushi/vec4 0, 0, 2;
%store/vec4 v00000229acd79290_0, 0, 2;
%pushi/vec4 0, 0, 8;
%store/vec4 v00000229acd798d0_0, 0, 8;
%end;
.thread T_2;
.scope S_00000229acd193c0;
T_3 ;
%wait E_00000229accfc4e0;
%load/vec4 v00000229acd79290_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_3.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_3.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_3.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_3.3, 6;
%jmp T_3.4;
T_3.0 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000229acd0df10_0, 0;
%load/vec4 v00000229acd79dd0_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_3.5, 8;
%pushi/vec4 1, 0, 2;
%assign/vec4 v00000229acd79290_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000229accd6a10_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000229acd00f00_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000229acd79470_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000229acd0df10_0, 0;
T_3.5 ;
%jmp T_3.4;
T_3.1 ;
%load/vec4 v00000229accd6a10_0;
%pad/u 32;
%cmpi/u 350, 0, 32;
%jmp/0xz T_3.7, 5;
%load/vec4 v00000229accd6a10_0;
%addi 1, 0, 16;
%assign/vec4 v00000229accd6a10_0, 0;
%jmp T_3.8;
T_3.7 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000229accd6a10_0, 0;
%pushi/vec4 2, 0, 2;
%assign/vec4 v00000229acd79290_0, 0;
T_3.8 ;
%jmp T_3.4;
T_3.2 ;
%load/vec4 v00000229accd6a10_0;
%pad/u 32;
%cmpi/u 233, 0, 32;
%jmp/0xz T_3.9, 5;
%load/vec4 v00000229accd6a10_0;
%addi 1, 0, 16;
%assign/vec4 v00000229accd6a10_0, 0;
%jmp T_3.10;
T_3.9 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000229accd6a10_0, 0;
%load/vec4 v00000229acd79dd0_0;
%ix/load 5, 0, 0;
%ix/getv 4, v00000229acd00f00_0;
%assign/vec4/off/d v00000229acd798d0_0, 4, 5;
%load/vec4 v00000229acd00f00_0;
%addi 1, 0, 4;
%assign/vec4 v00000229acd00f00_0, 0;
%load/vec4 v00000229acd00f00_0;
%pad/u 32;
%cmpi/e 7, 0, 32;
%jmp/0xz T_3.11, 4;
%pushi/vec4 3, 0, 2;
%assign/vec4 v00000229acd79290_0, 0;
T_3.11 ;
T_3.10 ;
%jmp T_3.4;
T_3.3 ;
%load/vec4 v00000229accd6a10_0;
%pad/u 32;
%cmpi/u 233, 0, 32;
%jmp/0xz T_3.13, 5;
%load/vec4 v00000229accd6a10_0;
%addi 1, 0, 16;
%assign/vec4 v00000229accd6a10_0, 0;
%jmp T_3.14;
T_3.13 ;
%pushi/vec4 0, 0, 2;
%assign/vec4 v00000229acd79290_0, 0;
%load/vec4 v00000229acd798d0_0;
%assign/vec4 v00000229acd0de70_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000229acd79470_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000229acd0df10_0, 0;
T_3.14 ;
%jmp T_3.4;
T_3.4 ;
%pop/vec4 1;
%jmp T_3;
.thread T_3;
.scope S_00000229acd190a0;
T_4 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000229acd79b50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000229acd79150_0, 0, 1;
%pushi/vec4 0, 0, 8;
%store/vec4 v00000229acd790b0_0, 0, 8;
%end;
.thread T_4;
.scope S_00000229acd190a0;
T_5 ;
%delay 10000, 0;
%load/vec4 v00000229acd79b50_0;
%inv;
%store/vec4 v00000229acd79b50_0, 0, 1;
%jmp T_5;
.thread T_5;
.scope S_00000229acd190a0;
T_6 ;
%vpi_call 2 39 "$display", "D\303\251but de la simulation" {0 0 0};
%vpi_call 2 40 "$dumpfile", "uart_loopback.vcd" {0 0 0};
%vpi_call 2 41 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000229acd190a0 {0 0 0};
%delay 200000, 0;
%pushi/vec4 165, 0, 8;
%store/vec4 v00000229acd790b0_0, 0, 8;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000229acd79150_0, 0, 1;
%delay 20000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000229acd79150_0, 0, 1;
T_6.0 ;
%load/vec4 v00000229acd7bd80_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%cmpi/ne 1, 0, 1;
%jmp/0xz T_6.1, 6;
%wait E_00000229accfc720;
%jmp T_6.0;
T_6.1 ;
%vpi_call 2 56 "$display", "Data envoyee : 0x%h", v00000229acd790b0_0 {0 0 0};
%vpi_call 2 57 "$display", "Data recue : 0x%h", v00000229acd79bf0_0 {0 0 0};
%load/vec4 v00000229acd79bf0_0;
%load/vec4 v00000229acd790b0_0;
%cmp/e;
%jmp/0xz T_6.2, 4;
%vpi_call 2 60 "$display", "Test reussi !" {0 0 0};
%jmp T_6.3;
T_6.2 ;
%vpi_call 2 62 "$display", "Test echoue..." {0 0 0};
T_6.3 ;
%delay 200000, 0;
%vpi_call 2 66 "$finish" {0 0 0};
%end;
.thread T_6;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"tb_top_uart_rx_tx.v";
"top_uart_rx_tx.v";
"uart_rx.v";
"uart_tx.v";