forked from tanchou/Verilog
Add UART transmitter module and testbench
- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate. - Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock. - Created a backup of the previous testbench (uart_tx_tb_old) for reference.
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14887
Semaine 1/UART/uart_loopback.vcd
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14887
Semaine 1/UART/uart_loopback.vcd
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